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Topic

Detection of Fraudulently Recycled Integrated Circuits

Department of Electrical and Computer Engineering

Date & location

• Wednesday, February 26, 2025

• 10:30 A.M.

• Virtual Defence

Reviewers

Supervisory Committee

• Dr. Mihai Sima, Department of Electrical and Computer Engineering, University of Victoria (Co-Supervisor)

• Dr. Stephen Neville, Department of Electrical and Computer Engineering, UVic (Co-Supervisor)

• Dr. Sudhakar, Department of Computer Science, UVic (Outside Member) 

External Examiner

• Dr. Violeta Petrescu, FH-Kärnten, University of Applied Science 

Chair of Oral Examination

• Dr. James Christian, School of Earth and Ocean Sciences, UVic

   

Abstract

As is true of many types of products, integrated circuits (ICs) are subject to counterfeiting. Of the various methods of counterfeiting ICs, recycling, where still functioning units are recovered from waste streams and passed off as new, is particularly problematic. These components are still functional but are unreliable due to their unknown operational histories. This poses an important risk to critical infrastructure in domains ranging from defense, to health care, to transportation. The long lifetimes of these systems makes it challenging to find suitable replacement ICs since the electronics industry evolves rapidly and produces parts with comparatively short production lives. A number of recycled integrated circuit (IC) risk mitigation approaches have been proposed, but these generally lack pragmatic feasibility. This work proposes a novel real-world deployable on-chip sensor that: 1. is tamper-resistant by exploiting persistent changes caused by hot carrier injection (HCI); 2. generates a DC signal measurable by common low-cost test equipment; and 3. reuses an existing I/O interface, including existing pins; while 4. requiring a very small footprint. Combining this sensor with a random sample-based testing strategy allows for low-cost and time efficient detection of fraudulently recycled batches of ICs. Through simulation-based validation using process-accurate models of a 65nm technology we show that employing a random sample size as small as 130 is sufficient for identifying such batches with a statistical significance level of 0.01.

The design of countermeasures against IC recycling requires the ability to simulate aging in CMOS devices. Electronic design automation tools commonly provide this ability; however, their models must be tuned for use with a specific target technology. This requires data which is ideally provided by a fab. It may also be collected from a set of purpose-built test devices, a costly and time-consuming process. This work describes a novel, low-cost, and rapid approach to tuning such models. It is an iterative method that leverages public domain data sourced from published studies to fit an aging model. Results are statistically validated against the target technology’s specification. The approach is demonstrated by fitting a compact hot carrier injection degradation model for use with both core and I/O nMOSFETs from a specific 65nm technology. Resulting model parameter values are validated with a maximum error of 0.5% with a 99% confidence bound.